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MCLK
24.576kHz
XOSC
XTAL
26MHz
≒8.192MHz
RCOSC
RTC Clock
32.768kHz
Divider
Divider
163.68MHz
196.416MHz
SYSPLL
Max199.2MHz
RF
1/250
Divider
Figure Clock and Reset-3 Clock Diagram
－47/1010－
Application Domain
163MHz(High performance mode)
/ 40MHz(Low Power mode)
Divider
Divider
Divider
49.104MHz
Divider
49.104MHz
Divider
System and IOP Domain
100MHz(High performance mode)
/ 32MHz(Low Power mode)
Divider
AHB
Divider
APB
Divider
Sensor Domain
GNSS Domain
100MHz(High performance mode)
/ 32MHz(Low Power mode)
Divider
66.4MHz(RFPLL)/65.472MHz(SYSPLL)
Divider
16.6MHz(RFPLL)/16.368MHz(SYSPLL)
Divider
Always On
32KHz / 8.192MHz
32KHz
CXD5602 User Manual
Application
Processor
AHB
APP Bus
Peripheral
CIS I/F
USB
SDIO
2D Graphics
eMMC
AUDIO
System and I/O
Processor
SYSIOP Bus
Peripheral
Debug
GNSS DSP
BB
ITP
PMU
RTC
- Quick Links:
- Cxd5602 Outline
- Block Diagram
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