Table of Contents
Advertisement
3.14 SYSIOP Clock and Reset Control
3.14.1
Function Overiew
The System and IOP Domain (referred to as "SYSIOP" hereinafter) is responsible for overall system control.
Centered around the Arm
I/F that supports I2C/SPI/UART, and the HOSTIFC, etc. for communication with the external host. These are
connected together via the SYSTEM Bus.
The performance such as the transfer rate depends on the combination of the X'tal Oscillator clock frequency and
voltage mode (High Performance mode/Low Power mode). The following describes a function overview using the
X'tal Oscillator clock frequency operating at 26 MHz as an example.
The SYSIOP offers the following functions.
System and I/O Processor
This is the processor block (referred to as "SYSCPU" hereinafter) that is centered around the Arm
The following functions are equipped.
®
®
Arm
Cortex
-M0+
The communication unit that performs communication between the Application Processor and CPU,
and between the GNSS DSP and CPU
Interrupt input register
Timer
®
AMBA
Design Kit (ADK) SP804
Two channel support
One Timer module for each processor (Total: Six Timers)
Watchdog Timer
®
AMBA
Design Kit (ADK) SP805
One channel for each processor (Total: Six Watchdog Timers)
System and I/O Processor Memory
256 KByte SRAM
operating frequency
High Performance mode: Up to 97.5 MHz
Low Power mode: Up to 32.5 MHz
SYSTEM Bus
A 32 bit multi-layer AHB bus matrix. Connects the blocks within the SYSIOP to each other and other Domains.
®
®
Cortex
-M0+, it equips IO Configuration, DMAC, RTC, a common communication
－931/1010－
CXD5602 User Manual
®
®
Cortex
-M0+.
- Quick Links:
- Cxd5602 Outline
- Block Diagram
Hide quick links:
Advertisement
Table of Contents
