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3.7.4
I2C4
The I2C4 is the I2C master and supports Standard and Fast Mode.
3.7.4.1 Register List
TTable I2C-82 shows a register list of the I2C4.
Address
Register Name
0x04106000
I2C4 registers (For details, refer to the API)
|
0x04106FFF
3.7.4.2 Clock and Reset
Figure I2C-41 shows the clock and reset system of the I2C4.
Before accessing the I2C4 registers, make sure to set CKSEL_PMU.SEL_RTC_PCLK=1'b0 and
SYSIOP_CKEN.APB=1'b1.
RCOSC
RTC_CLK_IN
XOSC
(32.768kHz)
SYSPLL
1/2
1/3
1/4
1/5
CKSEL_ROOT.CPU_PLL_DIV5
CKSEL_ROOT.RFPLL1_STAT_CLK_SEL4
CKSEL_ROOT.STAT_CLK_SEL4
CKDIV_CPU_DSP_BUS.CK_M0
CKDIV_CPU_DSP_BUS.CK_AHB
CKDIV_CPU_DSP_BUS.CK_APB
CKSEL_PMU.SEL_RTC_PCLK
PMU_CORE_CKEN.RTC_PCLK
PMU_CORE_CKEN.PMU_RTC_PCLK
Table I2C-74 I2C4 Register List
Type
Description
ck_cpu_bus
0
ck_rf_pll_1
1
1/M
2
3
0
1
2
3
0
1
Figure I2C-41 I2C4 Clock and Reset System
－218/1010－
ck_apb_gear
1/M
1/M
0
1
2
3
Reserved
Auto(PWD_SUB Power Domain ON)
SWRESET_BUS.XRST_PMU_I2CM
CXD5602 User Manual
initial
Value
-
I2C4
CK
I2CCLK
GATE
PCLK
PRESETn
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- Cxd5602 Outline
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