Table of Contents
Advertisement
Offset
Address
Name
(Transaction Port)
0x200
LPADC_A0
0x204
LPADC_A1
0x210
LPADC_D0
0x214
LPADC_D1
0x218
LPADC_D2
0x21C
LPADC_D4
0x220
LPADC_D5
0x224
LPADC_D6
0x240
HPADC_AC0
0x244
HPADC_AC1
0x250
HPADC_DC
0x280
HPADC0_A0
0x284
HPADC0_A1
0x288
HPADC0_A2
0x28C
HPADC0_A3
0x290
HPADC0_D0
0x294
HPADC0_D1
0x298
HPADC0_D2
0x2C0
HPADC1_A0
0x2C4
HPADC1_A1
0x2C8
HPADC1_A2
0x2CC
HPADC1_A3
0x2D0
HPADC1_D0
0x2D4
HPADC1_D1
0x2D8
HPADC1_D2
0x3D0
ADCIF_DCT
0x3D4
SCU_ADCIF_C
KPOWER
Table ADC-780 SCU_ADCIF_REG Register List
Type
Size
Description
(bits)
RW
32
LPADC enable control
RW
32
LPADC channel switching control
RW
32
LPADC software reset
RW
32
LPADC basic setting
RW
32
Permission/prohibition of the LPADC
ADC data acceptance
RW
32
LPADC basic setting
RW
32
LPADC basic setting
RW
32
LPADC basic setting
RW
32
HPADC common clock control
RW
32
HPADC common enable control
RW
32
Permission/prohibition of handling two
element vector
RW
32
HPADC0 clock selection
RW
32
HPADC0 enable control
RW
32
HPADC0 clock enable control
RW
32
HPADC0 LPF control
RW
32
HPADC0 software reset
RW
32
HPADC0 basic setting
RW
32
Permission/prohibition of the HPADC0
ADC data acceptance
RW
32
HPADC1 clock selection
RW
32
HPADC1 enable control
RW
32
HPADC1 clock enable control
RW
32
HPADC1 LPF control
RW
32
HPADC1 software reset
RW
32
HPADC1 basic setting
RW
32
Permission/prohibition of the HPADC1
ADC data acceptance
RO
32
SCU_ADCIF register map revision code
RW
32
－967/1010－
CXD5602 User Manual
Reset Value
0x00000000
0x00000000
0x00000000
0x00000008
0x00000000
0x00000008
0x00000008
0x00000008
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000100
0x00000000
0x00000010
0x00000000
0x00000000
0x00000000
0x00000000
0x00000100
0x00000000
0x00000010
0x00000000
0xADC1F000
0x00000001
- Quick Links:
- Cxd5602 Outline
- Block Diagram
Hide quick links:
Advertisement
Table of Contents
