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3.13.4.2
Function List
Table APP-782 shows the functions of the APP_DSP.
No
Function Name
ADSP
®
1
Cortex
-M4 processor with FPU
2
Processor ID
3
Interrupt Controller
4
Timer
5
Watchdog Timer
6
SLEEPING Signal Monitor
7
Debug Function
8
I/D Multiplexor
BUS
9
Address Map
10
Address Converter
11
Bus Matrix
12
Exclusive Load/Store
13
Protection and Error Information
Register
14
SYSIOP Bridge
15
ADMAC
Table APP-750 APP_DSP Function List
Description
The APP_DSP equips six Cortex
The APP_DSP has unique ID for each processor. Slave access control can be set for
each ID. The ID of each processor can be confirmed by reading registers.
This function controls interrupts which are input to each processor via Private
Peripheral Bus of Cortex
The Timer is used for general purpose, with two input ports, and can be controlled
via Private Peripheral Bus of the Cortex
The Watchdog Timer can be controlled via Private Peripheral Bus of the Cortex
processor with FPU.
This function enables to confirm the SLEEPING signal status of each processor by
reading registers.
The APP_DSP has the debug block which offers SWD, Trace, and Cross-Trigger
functions.
This function multiplexes ICode bus and DCode bus of the Cortex
with FPU in order of fixed priority (DCode has a higher priority than ICode).
The Address Map enables to access memories and control a variety of programable
functions via buses.
This function converts addresses of virtual memory space for every 64 Kbyte logical
area.
The Bus Matrix includes multi-layer matrix in the sub block based on the AMBA
AHB-Lite protocol and bridges which connect AHBs between the blocks.
This function performs monitoring and controlling of exclusive accesses to a specific
SRAM Tile.
This function blocks accesses from unprivileged bus masters to a specific bus slave,
or a bus slave which is in the status that the power is turned off. The function has a
register to hold access error information when an unprivileged access occurs.
Bus Matrix of the APP SUB Bus connects to the upper-layer SYSIOP bus of the
APP_DSP block via the asynchronous bridge.
Refer to the Section of the DMAC (3.8).
－908/1010－
®
-M4 processors with FPU in total.
®
-M4 processors with FPU.
®
-M4 processor with FPU
CXD5602 User Manual
®
-M4
®
-M4 processor
®
3
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