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3.9.12
SCU Register Details
3.9.12.1
Address Offset
The following shows 32 bit address offset from the CPU. Add the following address to the offsets in the table to
calculate the address from the CPU.
Offset: 0x00190000 (Mirror: 0x04190000)
3.9.12.2
SCU_REG Internal Memory List
Offset
Address
(Transaction Port)
0x0000 .. 0x3FFC
0x4000 .. 0x4FFC
3.9.12.3
SCU_REG Register List
Note: Some offset addresses are listed irregularly. Be careful when you set address by calculating with the SW.
The Reserved regions are secured in the 0x50AC to 0x50AF, and 0x50C0 to 0x50CF offset addresses shown in
the following list.
Offset
Name
Address
(Transaction
Port)
0x5018
I2C0
0x501C
I2C1
0x5020
SEQ_ENABLE_ALL
Table SCU (Sensor Control Unit)-107 SCU Internal Memory
Name
SEQ_IRAM
SEQ_DRAM(SCU_RAM)
Table SCU (Sensor Control Unit)-108 SCU Register List
Type
RO
RO
RW
－311/1010－
Size (bits)
Description
32
Inst Ram Array
Internal
Sequencer
Array
32
Internal Sequencer Data Ram Array
Size
Description
(bit)
32
Monitors SCL/SDA/internal status of
the IP for I2C0
32
Monitors SCL/SDA/internal status of
the IP for I2C1
32
Permission/prohibition
operations of whole sequencers can be
collectively controlled
0: operation is prohibited
1: operation is permitted
CXD5602 User Manual
Instruction
Ram
Reset Value
0x00000000
0x00000000
setting
for
0x00000000
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