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0x0E011020
CKEN_EMMC
0x0E011030
RESET
gear_n_img_
RW
[16]
wspi
Reserved
RO
[15:4]
gear_m_img_
RW
[3:0]
wspi
Reserved
RO
[31:3]
cken_emmc_s
RW
[2]
mp
cken_emmc_d
RW
[1]
rv
cken_emmc_c
RW
[0]
lkin
Reserved
RO
[31:23]
xrs_dsp_gen
RW
[22]
xrs_dsp5
RW
[21]
xrs_dsp4
RW
[20]
xrs_dsp3
RW
[19]
xrs_dsp2
RW
[18]
xrs_dsp1
RW
[17]
－902/1010－
CXD5602 User Manual
0
Division ratio setting of SPI5 clock
(numerator)
0: Clock stopped
1: Clock supplied
0
Reserved
4'h4
Division ratio setting of SPI5 clock
(denominator)
"0" must not be written.
0
Reserved
0
eMMC Sample Clock Enabler
0: Clock stopped
1: Clock supplied
0
eMMC DRV Clock Enabler
0: Clock stopped
1: Clock supplied
0
eMMC Clock Enabler
0: Clock stopped
1: Clock supplied
0
Reserved
0
DSP GENERAL/Reset Register
0: Reset assert
1: Reset release
0
Reset Register for ADSP5
0: Reset assert
1: Reset release
0
Reset Register for ADSP4
0: Reset assert
1: Reset release
0
Reset Register for ADSP3
0: Reset assert
1: Reset release
0
Reset Register for ADSP2
0: Reset assert
1: Reset release
0
Reset Register for ADSP1
0: Reset assert
1: Reset release
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