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3.14.3.6
Reset and Control
3.14.3.6.1
SYSIOP Reset Configuration Diagram
Figure SYSIOP Clock and Reset Control-117 SYSIOP Reset Configuration Diagramshows the reset configuration
diagram of SYSIOP.
SFC_HCLK
RW
Reserved
RW
I2CM_SUB
RW
SPIM
RW
UART1
RW
AHB_DMAC3
RW
COM_BRG
RW
AHB_BRG_COM
RW
IF
－949/1010－
[7]
1
Indicated as CG(SUB07) in
SYSIOP
Control-116
Clock enable for AHB synchronous
bridge between SYSTEM Bus and SPI
Flash Controller
[6]
0
Reserved
[5]
0
Indicated as CG(SUB05) in
SYSIOP
Control-116
Clock enable for I2C2
[4]
0
Indicated as CG(SUB04) in
SYSIOP
Control-116
Clock enable for SPI0
[3]
0
Indicated as CG(SUB03) in
SYSIOP
Control-116
Clock enable for UART1
[2]
0
Indicated as CG(SUB02) in
SYSIOP
Control-116
Clock enable for SYSUBDMAC
[1]
0
Indicated as CG(SUB01) in
SYSIOP
Control-116
Clock enable for AHB asynchronous
bridge master of I2C2, UART1, and SPI0
[0]
0
Indicated as CG(SUB00) in
SYSIOP
Control-116
Clock enable for AHB asynchronous
bridge slave of I2C2, UART1, and SPI0
CXD5602 User Manual
Figure
Clock
and
Reset
Figure
Clock
and
Reset
Figure
Clock
and
Reset
Figure
Clock
and
Reset
Figure
Clock
and
Reset
Figure
Clock
and
Reset
Figure
Clock
and
Reset
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