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0x041004D0
CKSEL_S
YSIOP_S
UB
3.14.3.4
Clock Frequency Division Switching Confirmation
3.14.3.4.1
Function Details
Using the API, the frequency division ratio of the target clock can be changed. You can confirm the currently
selected frequency division ratio from the register.
Clock Frequency Division for the System and I/O Processor, AHB, and APB
The clock (ck_cpu_bus_gear_1) for the System and I/O Processor, the AHB clock (ck_ahb_gear), and the APB
clock (ck_apb_gear) are frequency divided clocks of the ck_cpu_bus. The frequency division of the ck_cpu_bus is
described by the following equations.
SEL_UART0
RW
[8]
Reserved
RO
[7:3]
SEL_HOST2
RW
[2]
SEL_HOST
RW
[1:0]
Reserved
RO
[31:1]
SEL_UART1
RW
[0]
－939/1010－
0
Indicated as SEL(2) in
Reset Control-116
UART0 clock source switching
0: The clock selected by
CKSEL_SYSIOP.SEL_HOST2
1: Reserved
0
Reserved
0
Indicated as SEL(1) in
Reset Control-116
HOSTIFC clock source switching
0:
The
CKSEL_SYSIOP.SEL_HOST
1: XOSC
2'b00
Indicated as SEL(0) in
Reset Control-116
HOSTIFC clock source switching
2'b00: RCOSC
2'b01: RCRTC (RCOSC frequency divided by 250)
2'b10:
The
CKSEL_ROOT.SEL_RF_PLL_1_DIV
2'b11: RTC Clock
0
Reserved
0
Indicated as SEL(6) in
Reset Control-116
UART1 clock source switching
1: Reserved
0: The clock selected by CKDIV_COM.CK_COM
CXD5602 User Manual
Figure SYSIOP Clock and
Figure SYSIOP Clock and
clock
selected
Figure SYSIOP Clock and
clock
selected
Figure SYSIOP Clock and
by
by
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- Block Diagram
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