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APPDSP_RAMMODE_SEL1=0x0200000C (SRAM (Application Processor Tile #7) =ON)
APPDSP_RAMMODE_SEL1=0x04000030 (SRAM (Application Processor Tile #8) =ON)
APPDSP_RAMMODE_SEL1=0x080000C0 (SRAM (Application Processor Tile #9) =ON)
APPDSP_RAMMODE_SEL1=0x10000300 (SRAM (Application Processor Tile #10) =ON)
APPDSP_RAMMODE_SEL1=0x20000C00 (SRAM (Application Processor Tile #11) =ON)
2. Interrupt clear
PMU_INT_CLR.CLR[1:0]=2'b11
3. Interrupt mask setting
PMU_INT_MASK.MSK[1:0]=2'b00
4. Power supply control execution
PMU_PW_CTL.POWER_CTRL_ON=1
5. Interrupt confirmation
Confirm PMU_INT_STAT.STAT[1:0]=2'b01
6. Interrupt clear
PMU_INT_CLR.CLR[1:0]=2'b11
7. Clock and reset control
Perform proper clock and reset control according to each power domain, SRAM, and Analog circuits.
8. Turn OFF all SRAMs other than the power supply control setting SRAM (Application Processor Tile #4)
APPDSP_RAMMODE_SEL0=0x2F00CFF (SRAM (Application Processor Tile #0-3, 5) =OFF)
APPDSP_RAMMODE_SEL1=0x3F000000 (SRAM (Application Processor Tile #6-11) =OFF)
9. Interrupt clear
PMU_INT_CLR.CLR[1:0]=2'b11
10. Interrupt mask setting
PMU_INT_MASK.MSK[1:0]=2'b00
11. Power supply control execution
PMU_PW_CTL.POWER_CTRL_ON=1
12. Interrupt confirmation
Confirm PMU_INT_STAT.STAT[1:0]=2'b01
13. Interrupt clear
PMU_INT_CLR.CLR[1:0]=2'b11
3.4.5.2 Application Processor Sleep/Wakeup Control
In this document, the term Sleep refers to cases when any of the power domains of the CXD5602 turn OFF, or
when the DSP belonging to that power domain is not operating. On the other hand, Wakeup refers to cases when
they turn ON, or when the DSP belonging to that power domain starts operating. Since the Application Processor
of the PWD_APP_DSP cannot perform Sleep/Wakeup of its own power domain (PWD_APP_DSP),
Sleep/Wakeup is performed from the System and I/O Processor instead.
The following describes an overview and the control flow of Sleep/Wakeup of the PWD_APP_DSP. Also, Figure
－155/1010－
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