Sony CXD5602 User Manual page 940

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Frequency division of ck_cpu_bus
ck_cpu_bus_gear_1= frequency division (A)
ck_ahb_gear
ck_apb_gear
(C)
Note:
Refer to Table SYSIOP Clock and Reset Control-803 for frequency division (A), Table SYSIOP Clock
and Reset Control-804 for frequency division (B), and Table SYSIOP Clock and Reset Control-805 for
frequency division (C).
Table SYSIOP Clock and Reset Control-763 System and I/O Processor Frequency Division Setting
CKDIV_CPU_DSP_BUS.CK_M0
0
1
2
3
...
28
29
30
31
Table SYSIOP Clock and Reset Control-764 AHB Clock Frequency Division Setting
CKDIV_CPU_DSP_BUS.CK_AHB
0
1
2
3
4
5
6
7
Table SYSIOP Clock and Reset Control-765 APB Clock Frequency Division Setting
CKDIV_CPU_DSP_BUS.CK_APB
0
1
2
= frequency division (A) x frequency division (B)
= frequency division (A) x frequency division (B) x frequency division
Frequency Division(A)
1
2
3
4
Register value + 1
29
30
31
32
Frequency Division(B)
1
2
4
8
16
Prohibited setting
Frequency Division(C)
1
2
4
-940/1010-
CXD5602 User Manual

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