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3.8.3.2 Register Descriptions
Table DMAC-85 shows descriptions of the registers added to the SDMAC.
Address
Register Name
0x04120050
dma_done
0x04120054
dma_err
3.8.3.3 Clock and Reset
Figure DMAC-43 shows the clock and reset system diagram of the SDMAC.
Reset of the SDMAC is automatically released when the PWD_SYSIOP power domain is turned ON.
RTC_CLK_IN
(32.768kHz)
SYSPLL
1/2
1/3
1/4
1/5
CKSEL_ROOT.CPU_PLL_DIV5
CKSEL_ROOT.RFPLL1_STAT_CLK_SEL4
CKSEL_ROOT.STAT_CLK_SEL4
CKDIV_CPU_DSP_BUS.CK_M0
CKDIV_CPU_DSP_BUS.CK_AHB
SYSIOP_CKEN.AHB_DMAC0
Table DMAC-77 SDMAC Added Registers
Bit Field
Type
Bit
Name
dma_done
RW
[31:0]
dma_err
RW
[31:0]
RCOSC
ck_cpu_bus
0
ck_rf_pll_1
1
1/M
2
XOSC
3
0
1
2
3
0
1
Figure DMAC-43 SDMAC Clock and Reset System
－224/1010－
Initial
Description
Value
0x0
DMA channel number of DMA transfer completion
Read as:
0: DMA transfer not completed
1: DMA transfer completed
Write as:
0: No effect
1: Set dma_done LOW
0x0
DMA channel number of AHB error occurrence
Read as:
0: AHB no error occurred
1: AHB error occurred
Write as:
0: No effect
1: Set dma_err LOW
ck_ahb_gear
1/M
Auto(PWD_SYSIOP Power Domain ON)
CXD5602 User Manual
SDMAC
CK
HCLK
GATE
HRESETn
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