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PrimeCell
UART (PL011)
Communication speeds
High Performance mode: up to 3 Mbit/s
Low Power mode: up to 2 Mbit/s
DMAC
ADMAC (PL081) supports for memory to memory
IDMAC (like PL080) supports for SPI for display and UART for BT, BLE, Wi-Fi
Audio Codec Domain
The key features are:
I2S Bus Interface supports:
Two I2S-bus for audio-codec interface with DMA-based operation
16/24 bit per channel data transfers
I2S, Left-justified data format
Various bit clock frequency and codec clock frequency support
Master clock:
High Performance mode: 256fs, 128fs, 64fs of bit clock frequency
Low power mode: 128fs, 64fs of bit clock frequency
Slave clock:
High Performance mode: 256fs, 128fs, 64fs of bit clock frequency
Low power mode: 128fs, 64fs of bit clock frequency
Sampling rate
High Performance mode
Low Power mode
Two channels each I2S interface
Unique Audio Data Format (Pulse Density Modulation) between CXD5602GF/GG and CXD5247GF
This part mainly explains the Application Processor and application memory. For explanations of other separate
functional blocks, refer to other sections.
3.13.2
Power Supply Control
The Application Domain is divided into four power domains: the PWD_APP, PWD_APP_DSP, PWD_APP_SUB,
Master mode: 192 kHz, 96 kHz, 48 kHz
Slave mode: 192 kHz, 96 kHz, 48 kHz, 44.1 kHz, 16 kHz, 8 kHz
Master mode: 96 kHz, 48 kHz
Slave mode: 96 kHz, 48 kHz, 44.1 kHz, 16 kHz, 8 kHz
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CXD5602 User Manual
- Quick Links:
- Cxd5602 Outline
- Block Diagram
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