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3.9.9.2 External Bus Transaction Generation
SEQUENCER
10 instruction group
assertion of
Trigger Singal
or
Interrupt
signal
SCU_REG
Figure SCU (Sensor Control Unit)-73 External Bus Transaction Generation
At the External Bus Transaction Generation process, the bus transaction can be controlled for each physical
interface according to the setting value written on the SCU_RAM.
The SPI and I2C (I2C0, I2C1) access sequencers can be issued by combining the below sequence commands.
TX_RX command
・In the case of SPI, the selected data is output from the MOSI terminal and up to 8 Bytes of data are
simultaneously captured from the MISO terminal.
・In the case of IC2, the selected data is either output to the I2C bus, or up to 8 Bytes of data are captured
from the I2C bus. The slave address (and R/W selected) is also output as data handled by the TX_RX
command.
・In the case of continuous transfers, the TX_RX command can be executed continuously for multiple times.
You can freely select whether to turn OFF the CS in the case of SPI, or send a Stop Condition in the case of
I2C.
WAIT command
・Waits for the specified time
These commands are interpreted by the internal sequencer, converted to the APB access processing of the SPI
or I2C, to perform the actual data transfer processing.
SPI Master
I2C Master 0
3 instruction group
request
Generate signal
Configuration
about request
to sequencer
for Startup
completion
notice
Configuration
Configuration
Data
Data
10 configuration
data set
－281/1010－
I2C Master 1
LPADC
Data
formatting
Read
and
Sensor
Control
Data
FIFO
Data formatting
10 configuration
data set
CXD5602 User Manual
HPADC0
HPADC1
MATH_PROC
SCU_FIFO
Writing to FIFO
Setting
16 configuration
data set
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