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3.4.4.1.3
SYSPLL
OFF => ON Control Flow
The following describes the flow to turn ON the power supply of the SYSPLL. As a precondition, perform the
control with the power supply of the XOSC turned ON, and the clock supplied to the SYSPLL
(XOSC_CTRL.IXO_LV_PLLCLK_EN=1).
1. SYSPLL division ratio setting
Refer
to
SYS_PLL_CTRL2.ISP_LV_SELRCDIV.
Refer
to
SYS_PLL_CTRL2.ISP_LV_SELFBDIV.
The frequency of the SYSPLL is determined by the frequency of the XOSC and register value. The
following describes the division ratio settings of the SYSPLL.
Table PMU (Power Management Unit)-50 SYSPLL Division Ratio Setting
XOSC
Frequency
[MHz]
16.368
19.2
26
32.736
52
2. SYSPLL power supply ON setting
ANA_PW_CTL=32'h00040004
3. Interrupt clear
PMU_INT_CLR.CLR[1:0]=2'b11
4. Interrupt mask cancel
PMU_INT_MASK.MSK[1:0]=2'b00
5. SYSPLL power supply ON control
PMU_PW_CTL.POWER_CTRL_ON=1
Table
PMU
(Power
Table
PMU
(Power
SYS_PLL_CTRL2.ISP_L
V_SELRCDIV[1:0]
0
0
1
0
1
1
1
1
3
3
Management
Unit)-50
Management
Unit)-50
SYS_PLL_CTRL2.ISP_L
V_SELFBDIV[2:0]
0
1
2
0
1
2
0
1
1
2
－149/1010－
CXD5602 User Manual
for
the
settings
for
the
settings
SYSPLL
Frequency
[MHz]
163.68
196.42
144.00
192.00
156.00
195.00
163.68
196.42
156.00
195.00
of
of
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