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3.8.5.3 Clock Supply Start and Stop
3.8.5.3.1
Clock Supply Start
Perform the following control to start supplying the HCLK clock of the SYDMAC.
1. Reset release
Automatically released when the PWD_SYSIOP power domain is turned ON.
2. Clock supply start
SYSIOP_CKEN.AHB_DMAC2=1'b1
3.8.5.3.2
Clock Supply Stop
Perform the following control to stop supplying the HCLK clock of the SYDMAC.
1. Clock supply stop
SYSIOP_CKEN.AHB_DMAC2=1'b0
3.8.6
SYSUBDMAC
3.8.6.1 Register List
Table DMAC-88 shows the registers that control the SYSUBDMAC.
Address
Register Name
0x04123000
PrimeCell
|
0x04123FFC
3.8.6.2 Clock and Reset
Figure DMAC-47 shows the clock and reset system diagram of the SYSUBDMAC.
Reset of the SYSUBDMAC is automatically released when the PWD_SYSIOP_SUB power domain is turned ON.
Table DMAC-80 SYSUBDMAC Control Register List
Type
Description
®
Single Master DMA Controller (PL081)
－228/1010－
register
CXD5602 User Manual
initial
Value
-
- Quick Links:
- Cxd5602 Outline
- Block Diagram
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