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0x041004C8
CKSEL_P
MU
RORTC_STAT_CLK
RO
_SEL2
Reserved
RW
RFPLL1_STAT_CLK
RO
_SEL4
Reserved
RW
CPU_PLL_DIV5
RW
Reserved
RW
Reserved
RO
SEL_RTC_PCLK
RW
－164/1010－
[13]
0
Indicated as SEL(3) in
Reset (Clock Reset Generator)-34
Clock source switching status for power
supply control
0: RCOSC
1: RTC Clock
[12]
0
Reserved
[11:10]
0
Indicated as SEL(2) in
Reset (Clock Reset Generator)-34
SYSPLL frequency division switching status
2'b00: No frequency division
2'b01: divided by 2 (Duty H:L=1:1)
2'b10: divided by 3 (Duty H:L=2:1)
2'b11: divided by 4 (Duty H:L=1:1) or
divided by 5 (Duty H:L=3:2)
[9:3]
0
Reserved
[2]
0
Indicated as SEL(1) in
Reset (Clock Reset Generator)-34
Either SYSPLL4 or 5 frequency division
switching status
0: divided by 4
1: divided by 5
[1:0]
0
Reserved
[31:2]
0
Reserved
[1:0]
0
Indicated as SEL(6) in
Reset (Clock Reset Generator)-34
I2C4 clock source switching status
2'b00: ck_apb_gear
2'b01: RTC Clock
2'b10: RCOSC
2'b11: Prohibited setting
CXD5602 User Manual
Figure Clock and
Figure Clock and
Figure Clock and
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