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High Performance mode: up to 3 Mbit/s
Low Power mode: up to 2 Mbit/s
SPI Flash Controller
The main memory interface that supports the Quad SPI FLASH. For details, refer to Section 3.10.
HOSTIFC
The I/F block for communication with the CXD5602's external host. In addition to supporting the I2C/UART/SPI
communication I/F, sequential control is also possible for reduced power consumption. For details, refer to
Section 0.
Debugger I/F
A debugger interface circuit. It has a user authentication function that uses a debug path.
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CXD5602 User Manual
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