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3.10 SPI
3.10.1
Features and Overview
The SPI of this LSI equips the
The SPI0 and SPI3 offer additional functions to the Chip Select control. For details, refer to the
Synchronous Serial Port (PL022)
SPI List
SPI0 (Power domain: PWD_SYSIOP_SUB)
Supports only the master mode.
There is only one line of Chip Select.
This is used for data transmit/receive (Tx&Rx mode).
SPI3 (Power domain: PWD_SCU)
Supports only the master mode. Since it has three lines of Chip Select, it can connect a maximum of
three sensors to the SPI bus. SPI is usually controlled from the SCU sequencer. When the SCU
sequencer is not used, communication can be performed via the SPI bus by directly controlling the
registers of the SPI from the SYSCPU. Since control from the sequencer and control from the SYSCPU
are exclusive, they cannot be performed simultaneously.
This is used for data transmit/receive (Tx&Rx mode).
SPI4 (Power domain: PWD_APP_SUB)
Supports only the master mode.
There is only one line of Chip Select.
This is used for data transmit/receive (Tx&Rx mode) or data transmit (Tx mode) only.
SPI5 (Power domain: PWD_APP_SUB)
Supports only the master mode.
There is only one line of Chip Select.
This is used for data transmit/receive (Tx&Rx mode)
Additional functions
The SPI0 and SPI3 offer the following additional functions to the
Additional functions
Chip Select function (SPI3)
By the addition of two lines of Chip Select signals, one Chip Select signal can be selected from the
total of three Chip Select signals. The selection of the Chip Select signal is done through exclusive
control.
®
PrimeCell
Synchronous Serial Port (PL022)
Technical Reference Manual.
－873/1010－
from ARM Limited.
®
PrimeCell
Synchronous Serial Port
CXD5602 User Manual
®
PrimeCell
(PL022).
- Quick Links:
- Cxd5602 Outline
- Block Diagram
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