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Programmable Counter
The programmable counter consists of a 2-modulus pre-scalar, a 4-bit and 12-bit programmable counter and a port that
controls these elements.
The programmable counter stops operation in the PLL off mode, and operates in the PLL on mode respectively. The
radiation and consumption current can be reduced when the programmable counter is used in combination with the 1-chip
tuner with a built-in 1/16 pre-scaler.
The frequency divided by the programmable counter is inputted to the phase comparator, and the phase difference from
the reference frequency is outputted from the phase comparator. The internal clock of the programmable counter can also be
used to detect phase difference of the phase comparator and the doubler clock for DC-DC converter for VT.
( → Refer to the sections on Reference frequency divider, DC-DC converter for VT and Phase comparator.)
1. Program Counter Control Port
The PLL mode selection port is used for setting the frequency dividing method, while the programmable counter port is
used for setting the frequency division number.
Selection of PLL mode
Y1
φL15(8)
HF
Programmable counters 1 to 4
φL15(A)
Y1
Y2
Y4
P0
P1
P2
LSB
Y1
φL16(F)
TA0
φΚ11(F)
PLL amplifier setting register
The selection of the PLL mode and setting of the frequency division number of programmable counter are assigned to
data port 6 that has been selected at the select port. These controls are accessed by using the OUT1 instruction with [CN =
5H] specified in the operand.
There are two types of frequency division methods; the direct frequency division method (LF mode) and the pulse
swallow method (HF mode). Select a method depending on the frequency to be used and the frequency division number
that has been set.
The programmable counter has 12 bits (P4 to P15) in the LF mode and 16 bits (P0 to P15) in the HF mode. The
frequency division number is specified by writing it to the MSB bit ( φ L15(D). Once the MSB bit is set, all the data of P0 to
P15 will be updated. Therefore, the MSB bit must be accessed and specified last, even when part of the data is changed.
The PLL input (OSCin) has an input amplifier. Set this amplifier gain at the PLL amplifier setting registers. Set all of
these registers to "1" (FH).
Set the Y8 bit of the PLL mode select port ( φ L15(8)) to "0".
Note:
Note:
All the PLL amplifier setting registars are set to "1" after a system reset.
Note:
In the PLL amplifier setting registers, the TA0 and TA1 bits are for the OSCin input amplifier gain
setting and the TA2 and TA3 bits are for the IFin input amplifier gain setting respectively.
Y2
Y4
Y8
∗
∗
O
Setting the frequency dividing method
φL15(B)
Y8
Y1
Y2
Y4
Y8
P3
P4
P5
P6
P7
Setting the frequency division number of the programmable counter
Y2
Y4
Y8
TA1
TA2
TA3
Set ALL "1" (FH)
99
0：LF mode
1：HF mode
φL15(C)
φL15(D)
Y1
Y2
Y4
Y8
Y1
P8
P9
P10 P11
P12 P13 P14 P15
TC9349AFG
Y2
Y4
Y8
MSB
2006-02-24
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