Toshiba TC9349AFG Manual page 40

Cmos digital integrated circuit silicon monolithic
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(5)
Backup circuit
Reset input
POWER
Example Capacitor Backup Circuit (1)
Reset input
POWER
Note: If backup operation using a CKSTP/WAIT instruction is available, use release signal input to perform the
release operation as necessary. Moreover, on execution of the CKSTP command, connect an external
capacitance of 4.7 mF or more for the V
Note: The diode shown in the circuit diagrams should be a Schottky diode with a low VF and a small reverse-
leakage current.
Recommended diodes: 1SS357, 1SS393
Note: Set the backup capacitor capacity value according to the required backup time.
Note: The "H" level of reset input requires the application of a V
impedance at the time of reset off.
Note: The V
pin power supply is a logic power supply with a timing circuit, ALU, data memory and all
CPU
registers. The V
CPU
50
V
PLL
62
RESET
V
C1
C2 V
DD
DB
2
3
4
5
0.47 µ F
Schottky diode
50
V
PLL
62
RESET
V
C1
C2 V
DD
2
3
4
0.47 µ F
Example Battery Backup Circuit (2)
pin resistance as in Example Capacitor Circuit (2) above.
CPU
pin power supply should usually be retained at the time of backup.
40
V
CPU
10
V
DB
CPU
5
10
Schottky diode
Release signal
input
level voltage. Therefore set high
CPU
TC9349AFG
2006-02-24

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