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Instruction
Skip
Mnemonic
Set
Function
SHRC M
RORC M
XCH
M
DAL ADDR3, r
DALR
WAIT
P
CKSTP
NOOP
Note: The lower 4 bits of the 10 bits of program memory specified by the DAL instruction (DAL ADDR2, r) are
addressed indirectly by the contents of the general register. The 13 bits of program memory specified by DALR
instruction are used for indirect addressing.
Note: The DAL address register (AR) is located on the I/O map. (Refer to Register Ports.)
Note: The DAL or DALR instruction run-time is two machine cycles.
Function
Operation
Shift memory bits to
0 → (M) b3 → (M) b2 →
right direction with
(M) b1 → (M) b0→ (CY)
carry
(M) b3 → (M) b2 →
Rotate memory bits
(M) b1→ (M) b0 →
to right direction
with carry
(CY)
(M) b3 ↔ (M) b0,
Exchange memory
(M) b2 ↔ (M) b1
bits mutually
Load program in
DATA ← [ADDR3 +
page 0 to DATA
(r)] P in page 0
register
(Note)
Load program
memory to DATA
register referring to
DATA ← [(AR)]P
DAL address
AR ← (AR) + 1
register, and
increment DAL
address register
At P = "0" H, the
condition is CPU
waiting (soft wait
mode)
At P = "1" H, all
Wait at condition P
functions except for
clock generator
enter the waiting
state (hard wait
mode)
Clock generator
Stop clock generator to
stop
MODE condition
No operation
22
Machine Language (16 Bits)
IC
A
(6 Bits)
(2 Bits)
111111
DR
111111
DR
111111
DR
111110
ADDR3 (6 bits)
⎯
111111
111111
P
⎯
111111
⎯
⎯
111111
TC9349AFG
B
C
(4 Bits)
(4 Bits)
DC
0000
DC
0001
DC
0110
RN
⎯
1000
⎯
0100
⎯
0101
⎯
1111
2006-02-24
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