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I/O Map, Data Select Port (φL/K1A)
All the ports within the device are expressed with a matrix of six I/O instructions (OUT1 to 3 instructions and IN1 to 3
instructions) and 4-bit code numbers.
The allocation of these ports is shown on the following page in the form of an I/O map. The ports used in the execution
of the various I/O instructions on the horizontal axis of the I/O map are allocated to the port code numbers indicated on the
vertical axis. The G-register, data register and DAL bits are also used as ports.
The OUT1 to 3 instructions are specified as output ports, and the IN 1 to 3 instructions are specified as input ports.
Note: The ports indicated by the angled lines on the I/O map do not actually exist within the device.
When data is output to a non-existing output port by execution of the output instruction, the contents of
other ports and data memories are not affected. When a non-existing input port is specified by execution
of an input instruction, the data loaded from the data memory assumes "don't care" status.
Note: The output ports marked with an asterisk (*) on the I/O map are not used. Data output to these ports
assumes "don't care" status.
Note: The Y1 contents of the ports expressed in 4 bits correspond to the LSB and the Y8 contents correspond
to the MSB in the data memory.
The ports specified with the six I/O instructions and code number C are coded in the following manner.
φ [K/L] m n (o) (Pp)
Example:
The setting for the G-register is allocated to code 8 and 9 in the OUT1 instruction. The encoded expression at
this time becomes φL18 and φL19.
Pages (1 to 3)
Contents of selected port (indirectly specified data, 0 to F (HEX))
I/O instruction operand CN (0 to F (HEX))
The six I/O instructions are coded with digits 1 to 3
I/O instruction
OUT1
m
1
Indicates input/output ports.
K: Input port (instructions IN1 to 3)
L: Output port (instructions OUT1 to 3)
23
OUT2
OUT3
IN1
2
3
1
TC9349AFG
IN2
IN3
2
3
2006-02-24
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