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(2)
Example of serial mode setting in the 2-wire mode
Setting bit
M0, M1
CK0, CK1, OSC0, OSC1
MASTER
POL
NchS
SIS
STPS
SWENA
MSB
SOS
STA0~3
STP0~3
PSEL, SIO
ストップ
Stop
コンディション
condition
condition
Serial clock
シリアルクロック
(SCK2)
（ SCK2)
シリアル入出力
Serial input/output
（ SDIO2)
(SDIO2)
Execution of
命令の実行
instruction
シリアル出力
Serial output
カウンタ
E
counter
（
OTC0 OTC3)
～
(OTC0 to OTC3)
シリアル入力
Serial input
カウンタ
E
counter
（
ITC0 ITC3)
～
(ITC0 to ITC3)
BUSY1
BUSY2
RX F/F
The start condition (STA1 = "1") cannot be outputted at the ACK input/output timing during
Note:
2-wire operation (BUSY2 = "1") in the master mode. Output the stop condition, and then the
start condition.
2-wire setting (M0 = 0, M1 = 1)
Serial clock frequency setting
Master setting (MASTER = 1): Refer to an example of master operation timing.
Slave setting (MASTER = 0): Refer to an example of slave operation timing.
Serial clock stop state = H 、
Data output at the falling edge and data input at the rising edge (POL = 1 )
N-ch open drain setting (NchS = 1)
Setting of SDIO pin to serial input (SIS = 0)
Setting of stop condition to input counter (STPS = 1)
Stop weight enabled (SWENA = 1)
Output beginning with the most significant bit (MSB = 1)
Data output: SOS = 1, Data input: SOS = 0
Serial input/output start data: 7h
Serial input/output stop data: Eh
Select N-ch open-drain pin (SDIO2, SCK2) (PSEL = 1, SIO = 1)
スタート
Start
コンディション
SI7/SO7
SI6/SO6
SI0/SO0
７
６
０
７
６
５
０
84
Condition setting data
SCK端子より"L"レベルを出力してシリアル
SCK pin outputs the "L" level to forcibly
クロックを強制停止状態にします
。
stop the serial clock
SIF/SOF ACK
（
）
SI7/SO7
SI6/SO6
SI0/SO0
F
７
６
F
７
６
５
０
TC9349AFG
ストップ
Stop
コンディション
condition
SIF/SOF ACK
（
）
０
F
E
F
E
2006-02-24
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