Toshiba TC9349AFG Manual page 5

Cmos digital integrated circuit silicon monolithic
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Description of Pin Functions
PIN No.
Symbol
64
Xin1
1
Xout1
68
GND
2
VDD
3
C1
4
C2
Doubler output pins for
5
VDB
Pin Name
Function and Operation
Crystal oscillator pins.
Crystal oscillator pin
A reference 75 kHz crystal resonator is
connected to the Xin1 and Xout1 pins.
Power supply pin for the crystal oscillator
and doubler circuit for the CPU (V
Normally, V
DD
V
potential is detected in the 0.850 V to
DD
1.225 V range in 25 mV steps using the
decreased voltage detection circuit. If V
potential falls below the voltage being set,
Power-supply pins
the CPU can be stopped to prevent
incorrect operation.
Note: After reset, the voltage set for the
decreased voltage detection is V
= 0.85 V. CPU stop function is
enabled.
Doubler output pins for CPU.
The doubler system is the charge-pump
system.
When a doubler clamp is permitted, a
voltage of 2.0 V, 2.5 V or 3.0 V can be
selected. A doubler clock can select either
one of 75 kHz, 37.5 kHz or high-speed
oscillator clock.
Usually, the V
capacitor for stabilization (0.1 µF, 10 µF
typ.) supplies voltage for the power supply
of the CPU only ( V
is supplied to the power supply of the A/D
CPU
converter, and a 1.5 V constant-voltage
circuit ( V
).
EE
The voltage is doubled by the doubler
capacitor between C1 and C2 (0.47 µF
typ.). When the doubler clamp is enabled,
the voltage is doubled below the voltage
being set.
Note: During reset or execution of the
clock stop instruction, the V
set to V
level for CMOS output, and at high
impedance for open-drain output.
).
DB
= 0.9 to 1.8 V is applied.
DD
DD
pin connected to the
DB
). The V
potential
CPU
DB
pin is
DB
level. The LX pin is L
DD
5
TC9349AFG
Remarks
X
R
out1
out1
R
fXT1
V
DD
X
in1
(X
, X
)
in1
out1
GND
V
DD
V
DB
2006-02-24

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