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φL11(F) (decreased voltage control 2)
Y1
Y2
STOP
INT LB
F/F
SEL
Reset
Y1
Y2
STOP
φ
K26
F/F
Note: The STOP F/F changes to the reset state, with a CPU standby interval (100 ms), after system reset; after
release of the CKSTP instruction; and after detection of power off using the power-off detection circuit.
Y4
Y8
TIM
BREAK
SEL
ENA
Power supplies off break enable/power off function enable
0: Prohibition
1: Enable
(Note) If not using this function, set this bit to "0" for consumption current
Selection of decreased voltage detection operating timing
0: Detection is performed at a rate of once every 2 instruction cycles.
1: Detection is performed at a rate of once every 16 instruction cycles.
(Note) If this bit is set to "1", the consumption current of this function can
Permission of interruption by decreased voltage detection
0: Serial interface or timer port
1: Decreased voltage detection
Reset execution of decreased voltage detection F/F and power
supply OFF F/F:
Y4
Y8
V
DD
OFF
0
F/F
Power supply off detection flag
0: Power supply off not detected
1: Power supply off detected
Decreased power supply detection flag
0: Over the decreased voltage detection setting voltage
1: Under the decreased voltage detection setting voltage
38
Function stop
Function operation
reduction.
be decreased.
(refer to the item on the interruption function)
Every time it is set to "1" decreased voltage F/F and power
supply OFF detection F/F are reset simultaneously.
TC9349AFG
2006-02-24
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