Toshiba TC9349AFG Manual page 35

Cmos digital integrated circuit silicon monolithic
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V
pin
CPU
V
pin
DD
X
pin
OUT1
CPU
operation
CKSTP pin
Example for Operating Timing by Power Supply Pin
Note: Release of the CKSTP instruction through on/off of the V
bit ( φ L11(F)) to be set to "1". When this function is enabled, about 10 μ A will be consumed in the V
pin if voltage is applied through the V
function should be prohibited if voltage is always impressed through the V
Note: It is necessary to retain the potential of the V
Note: Reset occurs if the V
(power-on reset).
2. Wait mode
Wait mode suspends system operations, maintains the internal status immediately prior to suspension and decreases
current consumption. This mode stops at the address for the execution of the WAIT instruction on execution of hard
and soft wait. On cancellation of wait mode, the next address is executed immediately, with no standby interval.
(1)
SOFT WAIT mode
Only CPU operations within the device are suspended when a WAIT instruction is executed in which [P = 0H] has
been specified in the operand. The crystal resonator and other elements will continue to operate normally at this time.
SOFT WAIT mode is efficient in reducing current consumption during clock operations when used in programs that
include clock functions.
The wait status applies whenever the WAIT instruction is executed. Wait mode is canceled on the following
conditions:
1) If there is a change in the input state of an I/O port (I/O ports 3, 4, 6, and 8) that has been set as a break pin and to
input. (Refer to the section on I/O ports.)
2) When the 2 Hz Timer F/F is set as "1"
Note: The backup state applies if the V
supply is enabled (BRAEK ENA bit ( φ L11(F)) = "1"). The state is released when the power supply is
turned on (at approximately 0.5 V or more). At this time, the CPU starts up after 100 ms of standby
time have elapsed.
Note: Current consumption will vary depending on the execution time of the CPU operation.
Clock stop
(backup)
Executing of
CKSTP instruction
pin during CKSTP instruction execution. For this reason, this
DD
CPU
pin level (typ: 0.3 V) falls to 0.75 V or below and the voltage is then applied
CPU
power supply pin goes off in wait mode when the V
DD
35
When a voltage of approx. 0.5 V or more is impressed,
it is released.
Standby
CPU
(about 100 ms)
operation
power supply pin requires the BREAK ENA
DD
pin power supply.
DD
pin. Provide backup using a capacitor or similar means.
TC9349AFG
GND
GND
Clock stop
Executing of
CKSTP instruction
CPU
power
DD
2006-02-24

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