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2. Interrupt Reception Processing
The interrupt request is held until interruption is received, it interrupts by system reset operation or the program and it
resets a latch to "0" through programming. Interrupt reception operation is as shown below.
1) Each item of peripheral hardware outputs each interrupt request and sets the interrupt latch to "1" if the interrupt
conditions are fulfilled.
2) If an interrupt enable flag corresponding to a particular interrupt factor or a master enable flag is set to "1", the
CPU receives its interrupt, and the corresponding interrupt latch is reset to "0".
3) Any interrupt with a priority level below the accepted interrupt factor is prohibited.
4) The contents of the address stack pointer (ASP) and the interrupt stack pointer (ISP) are adjusted by -1.
5) The contents of the program counter (PC) are evacuated to the address stack register. The contents of the carry flag
(Ca), G-register (G-REG), data selection and data register (DATA) are evacuated to the interrupt stack register. At
this time, the contents of the program counter change to the next address for the time the interrupt was received or
the next address for which interrupt was enabled.
6) The contents of the vector address corresponding to the received interrupt are transferred to the program counter.
7) The contents of the vector address are executed.
Steps 2) to 6) are executed in one instruction cycle. This instruction cycle is called an "interrupt cycle".
In the case of an interrupt enable period
EI
Instruction
instruction
IMF
( Master enable flag )
Interruption signal
Interrupt signal
Interruption signal
Interrupt signal
IL
(Interrupt latch)
( Interruption latch)
1 instruction
cycle
In the case of an interrupt retention period
Instruction
IMF
( Master enable flag )
Interruption signal
Interrupt signal
Interruption signal
Interrupt signal
IL
(Interrupt latch)
( Interruption latch)
Interruption enable period
Interrupt enable period
EI
instruction
Interruption enable period
Interrupt retention period
51
TC9349AFG
Interrupt
Interrupt
ion cycle
cycle
Interruption processing routine
Interrupt processing routine
Interruption reception
Interrupt reception
Interrupt
Interrupt
ion cycle
cycle
Interruption processing routine
Interrupt processing routine
Interruption reception
Interrupt reception
2006-02-24
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