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Philips Semiconductors
Volume 1
Table 87:
Desired
baudrate
7200
9600
19200
38400
56000
57600
112000
115200
224000
448000
[1]
[2]
[3]
9.3.6 UART0 Interrupt Enable Register (U0IER - 0xE000 C004, when
DLAB = 0)
The U0IER is used to enable UART0 interrupt sources.
Table 88:
Bit
0
1
2
7:3
User manual
Baudrates available when using 20 MHz peripheral clock (PCLK = 20 MHz)
MULVAL = 0 DIVADDVAL = 0
U0DLM:U0DLL
[2]
[1]
hex
dec
00AE
174
0082
130
0041
65
0021
33
0021
22
0016
22
000B
11
000B
11
0006
6
0003
3
Values in the row represent decimal equivalent of a 16 bit long content (DLM:DLL).
Values in the row represent hex equivalent of a 16 bit long content (DLM:DLL).
Refers to the percent error between desired and actual baudrate.
UART0 Interrupt Enable Register (U0IER - address 0xE000 C004, when DLAB = 0)
bit description
Symbol
Value
RBR
Interrupt
Enable
0
1
THRE
Interrupt
Enable
0
1
RX Line
Status
Interrupt
0
Enable
1
-
-
Rev. 01 — 12 January 2006
Optimal MULVAL & DIVADDVAL
[3]
% error
U0DLM:U0DLL
[1]
dec
0.2240
124
0.1600
93
0.1600
31
1.3760
12
1.4400
13
1.3760
19
1.4400
6
1.3760
4
7.5200
3
7.5200
2
Description
U0IER[0] enables the Receive Data Available interrupt
for UART0. It also controls the Character Receive
Time-out interrupt.
Disable the RDA interrupts.
Enable the RDA interrupts.
U0IER[1] enables the THRE interrupt for UART0. The
status of this can be read from U0LSR[5].
Disable the THRE interrupts.
Enable the THRE interrupts.
U0IER[2] enables the UART0 RX line status interrupts.
The status of this interrupt can be read from U0LSR[4:1].
Disable the RX line status interrupts.
Enable the RX line status interrupts.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
UM10161
Chapter 9: UART0
Fractional
% error
pre-scaler value
MULDIV
MULDIV + DIVADDVAL
5/(5+2)
0.0064
5/(5+2)
0.0064
10/(10+11)
0.0064
7/(7+12)
0.0594
7/(7+5)
0.0160
7/(7+1)
0.0594
7/(7+6)
0.1600
7/(7+12)
0.0594
7/(7+6)
0.1600
5/(5+2)
0.3520
Reset
value
0
0
0
NA
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
[3]
87
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