Table of Contents
Advertisement
Philips Semiconductors
Volume 1
Table 58:
Pin description
Symbol
LQFP48
[1]
P0.26/AD0.7
39
[4]
P0.27/TRST/
8
CAP2.0
[4]
P0.28/TMS/
9
CAP2.1
[4]
P0.29/TCK/
10
CAP2.2
[4]
P0.30/TDI/
15
MAT3.3
[4]
P0.31/TDO
16
[5]
RTXC1
20
[5]
RTXC2
25
[5]
RTCK
26
X1
11
X2
12
DBGSEL
27
RST
6
V
7, 19, 43
SS
31
V
SSA
V
42
DDA
V
5
DD(1V8)
V
17, 40
DD(3V3)
VBAT
4
[1]
5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.
User manual
...continued
PLCC44
Type
n.c.
I/O
I
[4]
13
I/O
I
I
[4]
14
I/O
I
I
[4]
15
I/O
I
I
[4]
20
I/O
I
O
[4]
21
O
O
[5]
24
I
[5]
29
O
n.c.
I/O
16
I
17
O
30
I
11
I
1, 12, 23
I
34
I
44
I
10
I
42
I
n.c.
I
Rev. 01 — 12 January 2006
Description
P0.26 — General purpose Input/output digital pin (GPIO).
AD0.7 — Analog Input 7.
P0.27 — General purpose Input/output digital pin (GPIO).
TRST — Test Reset for JTAG interface.
CAP2.0 — Capture input for Timer 2, channel 0.
P0.28 — General purpose Input/output digital pin (GPIO).
TMS — Test Mode Select for JTAG interface.
CAP2.1 — Capture input for Timer 2, channel 1.
P0.29 — General purpose Input/output digital pin (GPIO).
TCK — Test Clock for JTAG interface.
CAP2.2 — Capture input for Timer 2, channel 2.
P0.30 — General purpose Input/output digital pin (GPIO).
TDI — Test Data In for JTAG interface.
MAT3.3 — PWM output 3 for Timer 3.
P0.31 — General purpose output only digital pin (GPIO).
TDO — Test Data Out for JTAG interface.
Input to the RTC oscillator circuit.
Output from the RTC oscillator circuit.
Returned test clock output: Extra signal added to the JTAG
port. Assists debugger synchronization when processor
frequency varies. Bidirectional pin with internal pull-up.
Input to the oscillator circuit and internal clock generator
circuits.
Output from the oscillator amplifier.
Debug select: When LOW, the part operates normally. When
HIGH, debug mode is entered. Input with internal pull-down.
External reset input: A LOW on this pin resets the device,
causing I/O ports and peripherals to take on their default
states and processor execution to begin at address 0. TTL
with hysteresis, 5 V tolerant.
Ground: 0 V reference.
Analog ground: 0 V reference. This should be nominally the
same voltage as V
but should be isolated to minimize noise
SS
and error.
Analog 3.3 V power supply: This should be nominally the
same voltage as V
but should be isolated to minimize
DD(3V3)
noise and error. This voltage is used to power the on-chip
PLL.
1.8 V core power supply: This is the power supply voltage for
internal circuitry.
3.3 V pad power supply: This is the power supply voltage for
the I/O ports.
RTC power supply: 3.3 V on this pin supplies the power to
the RTC.
UM10161
Chapter 6: Pin configuration
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
64
Advertisement
Chapters
Table of Contents
