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Philips Semiconductors
Volume 1
can be a useful capability but intrinsically limits alternate uses for the same pins if the I
interface is not used. Seldom is this capability needed on multiple I
same microcontroller.
11.4 Pin description
Table 117: I
Pin
SDA0,1
SCL0,1
2
11.5 I
C operating modes
In a given application, the I
mode, the I
one of these addresses is detected, an interrupt is requested. If the processor wishes to
become the bus master, the hardware waits until the bus is free before the master mode is
entered so that a possible slave operation is not interrupted. If bus arbitration is lost in the
master mode, the I
own slave address in the same serial transfer.
11.5.1 Master Transmitter mode
In this mode data is transmitted from master to slave. Before the master transmitter mode
can be entered, the I2CONSET register must be initialized as shown in
must be set to 1 to enable the I
acknowledge any address when another device is master of the bus, so it can not enter
slave mode. The STA, STO and SI bits must be 0. The SI Bit is cleared by writing 1 to the
SIC bit in the I2CONCLR register.
User manual
I
2
C bus
SCL
SDA
LPC2101/02/03
2
Fig 23. I
C-bus configuration
2
C Pin Description
Type
Input/Output
Input/Output
2
C hardware looks for its own slave address and the general call address. If
2
C block switches to the slave mode immediately and can detect its
Rev. 01 — 12 January 2006
pull-up
pull-up
resistor
resistor
OTHER DEVICE WITH
2
I
C INTERFACE
Description
2
I
C Serial Data.
2
I
C Serial Clock.
2
C block may operate as a master, a slave, or both. In the slave
2
C function. If the AA bit is 0, the I
UM10161
2
Chapter 11: I
C interfaces
2
C interfaces within the
SDA
SCL
OTHER DEVICE WITH
2
I
C INTERFACE
Table
118. I2EN
2
C interface will not
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
2
C
120
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