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Philips Semiconductors
Volume 1
15.5.8 Match Control Register (MCR, TIMER0: T0MCR - 0xE000 4014 and
TIMER1: T1MCR - 0xE000 8014)
The Match Control Register is used to control what operations are performed when one of
the Match Registers matches the Timer Counter. The function of each of the bits is shown
in
Table 169: Match Control Register (MCR, TIMER0: T0MCR - address 0xE000 4014 and TIMER1: T1MCR - address
0xE000 8014) bit description
Bit
Symbol Value Description
0
MR0I
1
0
1
MR0R
1
0
2
MR0S
1
0
3
MR1I
1
0
4
MR1R
1
0
5
MR1S
1
0
6
MR2I
1
0
7
MR2R
1
0
8
MR2S
1
0
9
MR3I
1
0
10
MR3R
1
0
11
MR3S
1
0
15:12
-
User manual
Table
169.
Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
This interrupt is disabled
Reset on MR0: the TC will be reset if MR0 matches it.
Feature disabled.
Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches
the TC.
Feature disabled.
Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
This interrupt is disabled
Reset on MR1: the TC will be reset if MR1 matches it.
Feature disabled.
Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches
the TC.
Feature disabled.
Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
This interrupt is disabled
Reset on MR2: the TC will be reset if MR2 matches it.
Feature disabled.
Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches
the TC.
Feature disabled.
Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
This interrupt is disabled
Reset on MR3: the TC will be reset if MR3 matches it.
Feature disabled.
Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches
the TC.
Feature disabled.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Rev. 01 — 12 January 2006
UM10161
Chapter 15: Timer0 and Timer1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Reset
value
0
0
0
0
0
0
0
0
0
0
0
0
NA
193
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