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Philips Semiconductors
Volume 1
PCLK
prescale counter
timer counter
TCR[0]
(counter enable)
interrupt
Fig 55. A timer cycle in which PR=2, MRx=6, and both interrupt and stop on match are enabled
16.9 Architecture
The block diagram for TIMER/COUNTER2 and TIMER/COUNTER3 is shown in
Figure
User manual
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1
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56.
Rev. 01 — 12 January 2006
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UM10161
Chapter 16: Timer2 and Timer3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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