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12.4.3 SPI Data Register (S0SPDR - 0xE002 0008)
This bi-directional data register provides the transmit and receive data for the SPI.
Transmit data is provided to the SPI by writing to this register. Data received by the SPI
can be read from this register. When a master, a write to this register will start a SPI data
transfer. Writes to this register will be blocked from when a data transfer starts to when the
SPIF status bit is set, and the status register has not been read.
Table 143: SPI Data Register (S0SPDR - address 0xE002 0008) bit description
Bit
7:0
15:8 DataHigh
12.4.4 SPI Clock Counter Register (S0SPCCR - 0xE002 000C)
This register controls the frequency of a master's SCK. The register indicates the number
of PCLK cycles that make up an SPI clock. The value of this register must always be an
even number. As a result, bit 0 must always be 0. The value of the register must also
always be greater than or equal to 8. Violations of this can result in unpredictable
behavior.
Table 144: SPI Clock Counter Register (S0SPCCR - address 0xE002 000C) bit description
Bit
7:0
The SPI0 rate may be calculated as: PCLK / SPCCR0 value. The PCLK rate is
CCLK /APB divider rate as determined by the APBDIV register contents.
12.4.5 SPI Interrupt register (S0SPINT - 0xE002 001C)
This register contains the interrupt flag for the SPI0 interface.
Table 145: SPI Interrupt register (S0SPINT - address 0xE002 001C) bit description
Bit
Symbol
0
SPI Interrupt
Flag
7:1
-
12.5 Architecture
The block diagram of the SPI solution implemented in SPI0 interface is shown in the
Figure
User manual
Symbol
Description
DataLow
SPI Bi-directional data port.
If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some
or all of these bits contain the additional transmit and receive
bits. When less than 16 bits are selected, the more significant
among these bits read as zeroes.
Symbol
Description
Counter
SPI0 Clock counter setting.
Description
SPI interrupt flag. Set by the SPI interface to generate an interrupt. Cleared
by writing a 1 to this bit.
Note: this bit will be set once when SPIE = 1 and at least one of SPIF and
WCOL bits is 1. However, only when the SPI Interrupt bit is set and SPI0
Interrupt is enabled in the VIC, SPI based interrupt can be processed by
interrupt handling software.
Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
40.
Rev. 01 — 12 January 2006
UM10161
Chapter 12: SPI
Reset value
0x00
0x00
Reset value
0x00
Reset value
0
NA
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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