Table of Contents
Advertisement
Philips Semiconductors
Volume 1
3.8.7 PLL Feed register (PLLFEED - 0xE01F C08C)
A correct feed sequence must be written to the PLLFEED register in order for changes to
the PLLCON and PLLCFG registers to take effect. The feed sequence is:
The two writes must be in the correct sequence, and must be consecutive APB bus
cycles. The latter requirement implies that interrupts must be disabled for the duration of
the PLL feed operation. If either of the feed values is incorrect, or one of the previously
mentioned conditions is not met, any changes to the PLLCON or PLLCFG register will not
become effective.
Table 20:
Bit
7:0
3.8.8 PLL and Power-down mode
Power-down mode automatically turns off and disconnects activated PLL(s). Wake-up
from Power-down mode does not automatically restore the PLL settings. This must be
done in software. Typically, a routine to activate the PLL, wait for lock, and then connect
the PLL can be called at the beginning of any interrupt service routine that might be called
due to the wake-up. It is important not to attempt to restart the PLL by simply feeding it
when execution resumes after a wake-up from Power-down mode. This would enable and
connect the PLL at the same time, before PLL lock is established.
3.8.9 PLL frequency calculation
The PLL equations use the following parameters:
Table 21:
Element
F
F
CCLK
M
P
The PLL output frequency (when the PLL is both active and connected) is given by:
CCLK = M × F
The CCO frequency can be computed as:
F
User manual
1. Write the value 0xAA to PLLFEED.
2. Write the value 0x55 to PLLFEED.
PLL Feed register (PLLFEED - address 0xE01F C08C) bit description
Symbol
Description
PLLFEED The PLL feed sequence must be written to this register in order for
PLL configuration and control register changes to take effect.
Elements determining PLL's frequency
Description
the frequency from the crystal oscillator/external oscillator
OSC
the frequency of the PLL current controlled oscillator
CCO
the PLL output frequency (also the processor clock frequency)
PLL Multiplier value from the MSEL bits in the PLLCFG register
PLL Divider value from the PSEL bits in the PLLCFG register
or CCLK = F
OSC
= CCLK × 2 × P or F
CCO
Rev. 01 — 12 January 2006
/ (2 × P)
CCO
× M × 2 × P
= F
CCO
OSC
UM10161
Chapter 3: System control block
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Reset
value
0x00
29
Advertisement
Chapters
Table of Contents
