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Philips Semiconductors
Volume 1
The U0ACR AutoRestart bit can be used to automatically restart baud-rate measurement
if a time-out occurs (the rate measurement counter overflows). If this bit is set the rate
measurement will restart at the next falling edge of the UART0 Rx pin.
The auto-baud function can generate two interrupts.
The auto-baud interrupts have to be cleared by setting the corresponding U0ACR
ABTOIntClr and ABEOIntEn bits.
Typically the fractional baud-rate generator is disabled (DIVADDVAL = 0) during
auto-baud. However, if the fractional baud-rate generator is enabled (DIVADDVAL > 0), it
is going to impact the measuring of UART0 Rx pin baud-rate, but the value of the U0FDR
register is not going to be modified after rate measurement. Also, when auto-baud is used,
any write to U0DLM and U0DLL registers should be done before U0ACR register write.
The minimum and the maximum baudrates supported by UART0 are function of PCLK,
number of data bits, stop-bits and parity bits.
9.3.14 UART0 Transmit Enable Register (U0TER - 0xE000 C030)
LPC2101/02/03's U0TER enables implementation of software flow control. When
TXEn=1, UART0 transmitter will keep sending data as long as they are available. As soon
as TXEn becomes 0, UART0 transmission will stop.
Table 96
Table 96:
Bit
6:0
7
User manual
•
The U0IIR ABTOInt interrupt will get set if the interrupt is enabled (U0IER ABToIntEn
is set and the auto-baud rate measurement counter overflows).
•
The U0IIR ABEOInt interrupt will get set if the interrupt is enabled (U0IER ABEOIntEn
is set and the auto-baud has completed successfully).
× CLK
2 P
≤
ratemin
=
------------------------ -
UART0 baudrate
16 2 15
×
describes how to use TXEn bit in order to achieve software flow control.
UART0 Transmit Enable Register (U0TER - address 0xE000 C030) bit description
Symbol
Description
-
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
TXEN
When this bit is 1, as it is after a Reset, data written to the THR is output
on the TXD pin as soon as any preceding data has been sent. If this bit
is cleared to 0 while a character is being sent, the transmission of that
character is completed, but no further characters are sent until this bit is
set again. In other words, a 0 in this bit blocks the transfer of characters
from the THR or TX FIFO into the transmit shift register. Software
implementing software-handshaking can clear this bit when it receives
an XOFF character (DC3). Software can set this bit again when it
receives an XON (DC1) character.
Rev. 01 — 12 January 2006
PCLK
≤
----------------------------------------------------------------------------------------------------------- -
×
(
16
2
+
databits
+
paritybits
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
UM10161
Chapter 9: UART0
(3)
=
ratemax
)
+
stopbits
Reset
value
NA
1
94
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