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Philips Semiconductors
Volume 1
The PLL inputs and settings must meet the following:
3.8.10 Procedure for determining PLL settings
If a particular application uses the PLL, its configuration may be determined as follows:
Table 22:
PSEL Bits (PLLCFG bits [6:5])
00
01
10
11
Table 23:
MSEL Bits (PLLCFG bits [4:0])
00000
00001
00010
00011
...
11110
11111
3.8.11 PLL configuring examples
Example: an application configuring the PLL
System design asks for F
User manual
•
F
is in the range of 10 MHz to 25 MHz.
OSC
•
CCLK is in the range of 10 MHz to F
microcontroller - determined by the system microcontroller is embedded in).
•
F
is in the range of 156 MHz to 320 MHz.
CCO
1. Choose the desired processor operating frequency (CCLK). This may be based on
processor throughput requirements, need to support a specific set of UART baud
rates, etc. Bear in mind that peripheral devices may be running from a lower clock
than the processor (see
2. Choose an oscillator frequency (F
multiple of F
.
OSC
3. Calculate the value of M to configure the MSEL bits. M = CCLK / F
the range of 1 to 32. The value written to the MSEL bits in PLLCFG is M − 1 (see
Table
23.
4. Find a value for P to configure the PSEL bits, such that F
frequency limits. F
CCO
of the values 1, 2, 4, or 8. The value written to the PSEL bits in PLLCFG is 00 for
P = 1; 01 for P = 2; 10 for P = 4; 11 for P = 8 (see
PLL Divider values
PLL Multiplier values
Rev. 01 — 12 January 2006
(the maximum allowed frequency for the
max
Section 3.11 "APB divider" on page
). CCLK must be the whole (non-fractional)
OSC
is calculated using the equation given above. P must have one
Value of P
1
2
4
8
Value of M
1
2
3
4
...
31
32
= 10 MHz and requires CCLK = 60 MHz.
OSC
UM10161
Chapter 3: System control block
36).
. M must be in
OSC
is within its defined
CCO
Table
22).
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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