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Philips Semiconductors
Volume 1
Table 24:
Name
PCON
PCONP Power Control for Peripherals Register. This
[1]
3.9.2 Power Control register (PCON - 0xE01F COCO)
The PCON register contains two bits. Writing a one to the corresponding bit causes entry
to either the Power-down or Idle mode. If both bits are set, Power-down mode is entered.
Table 25:
Bit
0
1
7:2
3.9.3 Power Control for Peripherals register (PCONP - 0xE01F COC4)
The PCONP register allows turning off selected peripheral functions for the purpose of
saving power. This is accomplished by gating off the clock source to the specified
peripheral blocks. A few peripheral functions cannot be turned off (i.e. the watchdog timer,
GPIO, the Pin Connect block, and the System Control block). Some peripherals,
particularly those that include analog functions, may consume power that is not clock
dependent. These peripherals may contain a separate disable control that turns off
additional circuitry to reduce power. Each bit in PCONP controls one of the peripherals.
The bit numbers correspond to the related peripheral number as shown in the APB
peripheral map
maps" on page
If a peripheral control bit is 1, that peripheral is enabled. If a peripheral bit is 0, that
peripheral is disabled to conserve power. For example if bit 19 is 1, the I
enabled. If bit 19 is 0, the I
Important: valid read from a peripheral register and valid write to a peripheral
register is possible only if that peripheral is enabled in the PCONP register!
User manual
Power control registers
Description
Power Control Register. This register contains
control bits that enable the two reduced power
operating modes of the microcontroller. See
Table
25.
register contains control bits that enable and
disable individual peripheral functions,
Allowing elimination of power consumption by
peripherals that are not needed.
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
Power Control register (PCON - address 0xE01F COCO) bit description
Symbol
Description
IDL
Idle mode - when 1, this bit causes the processor clock to be stopped,
while on-chip peripherals remain active. Any enabled interrupt from a
peripheral or an external interrupt source will cause the processor to
resume execution.
PD
Power-down mode - when 1, this bit causes the oscillator and all
on-chip clocks to be stopped. A wake-up condition from an external
interrupt can cause the oscillator to restart, the PD bit to be cleared,
and the processor to resume execution.
-
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Table 2 "APB peripheries and base addresses"
8.
2
C1 interface is disabled.
Rev. 01 — 12 January 2006
UM10161
Chapter 3: System control block
Access Reset
Address
[1]
value
R/W
0x00
0xE01F C0C0
R/W
0x0018 17BE 0xE01F C0C4
in
Section 2.1 "Memory
2
C1 interface is
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Reset
value
0
0
NA
32
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