Table of Contents
Advertisement
Philips Semiconductors
Volume 1
Table 159: A/D Control Register (AD0CR - address 0xE003 4000 ) bit description
Bit
Symbol
Value Description
26:24 START
000
001
010
011
100
101
110
111
27
EDGE
1
0
31:28 -
14.4.2 A/D Global Data Register (AD0GDR - 0xE003 4004)
Table 160: A/D Global Data Register (AD0GDR - address 0xE003 4004 ) bit description
Bit
Symbol
5:0
-
15:6
RESULT
23:16
-
26:24
CHN
29:27
-
30
OVERUN
31
DONE
User manual
When the BURST bit is 0, these bits control whether and when an A/D conversion is
started:
No start (this value should be used when clearing PDN to 0).
Start conversion now.
Start conversion when the edge selected by bit 27 occurs on P0.16/EINT0/MAT0.2 pin.
Start conversion when the edge selected by bit 27 occurs on P0.22.
Start conversion when the edge selected by bit 27 occurs on MAT0.1.
Start conversion when the edge selected by bit 27 occurs on MAT0.3.
Start conversion when the edge selected by bit 27 occurs on MAT1.0.
Start conversion when the edge selected by bit 27 occurs on MAT1.1.
This bit is significant only when the START field contains 010-111. In these cases:
Start conversion on a falling edge on the selected CAP/MAT signal.
Start conversion on a rising edge on the selected CAP/MAT signal.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Description
Reserved, user software should not write ones to reserved bits. The value read from
a reserved bit is not defined.
When DONE is 1, this field contains a binary fraction representing the voltage on
the Ain pin selected by the SEL field, divided by the voltage on the V
(V/V
). Zero in the field indicates that the voltage on the Ain pin was less than,
REF
equal to, or close to that on V
close to, equal to, or greater than that on V
Reserved, user software should not write ones to reserved bits. The value read from
a reserved bit is not defined.
These bits contain the channel from which the RESULT bits were converted (e.g.
000 identifies channel 0, 001 channel 1...).
Reserved, user software should not write ones to reserved bits. The value read from
a reserved bit is not defined.
This bit is 1 in burst mode if the results of one or more conversions was (were) lost
and overwritten before the conversion that produced the result in the RESULT bits.
This bit is cleared by reading this register.
This bit is set to 1 when an A/D conversion completes. It is cleared when this
register is read and when the ADCR is written. If the ADCR is written while a
conversion is still in progress, this bit is set and a new conversion is started.
Rev. 01 — 12 January 2006
, while 0x3FF indicates that the voltage on Ain was
SSA
.
REF
UM10161
Chapter 14: A/D converter
Reset
value
NA
NA
pin
DDA
NA
NA
NA
0
0
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Reset
value
0
0
NA
183
Advertisement
Chapters
Table of Contents
