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Philips Semiconductors
Volume 1
Table 43:
Interrupt Enable register (VICIntEnable - address 0xFFFF F010) bit description
Bit
Symbol
31:0
See
VICIntEnable
bit allocation
table.
5.4.5 Interrupt Enable Clear register (VICIntEnClear - 0xFFFF F014)
This is a write only register. This register allows software to clear one or more bits in the
Interrupt Enable register (see
0xFFFF F010)" on page
Table 44:
Software Interrupt Clear register (VICIntEnClear - address 0xFFFF F014) bit allocation
Reset value: 0x0000 0000
Bit
31
Symbol
-
Access
WO
Bit
23
Symbol
-
Access
WO
Bit
15
Symbol
EINT1
Access
WO
Bit
7
Symbol
UART1
Access
WO
Table 45:
Software Interrupt Clear register (VICIntEnClear - address 0xFFFF F014) bit description
Bit
Symbol
31:0
See
VICIntEnClear
bit allocation
table.
5.4.6 Interrupt Select register (VICIntSelect - 0xFFFF F00C)
This is a read/write accessible register. This register classifies each of the 32 interrupt
requests as contributing to FIQ or IRQ.
Table 46:
Interrupt Select register (VICIntSelect - address 0xFFFF F00C) bit allocation
Reset value: 0x0000 0000
Bit
31
Symbol
-
Access
R/W
User manual
Description
When this register is read, 1s indicate interrupt requests or software interrupts
that are enabled to contribute to FIQ or IRQ.
When this register is written, ones enable interrupt requests or software
interrupts to contribute to FIQ or IRQ, zeroes have no effect. See
"Interrupt Enable Clear register (VICIntEnClear - 0xFFFF F014)" on page 49
and
Table 45
below for how to disable interrupts.
48), without having to first read it.
30
29
-
-
WO
WO
22
21
-
-
WO
WO
14
13
EINT0
RTC
WO
WO
6
5
UART0
TIMER1
WO
WO
Value
Description
0
Writing a 0 leaves the corresponding bit in VICIntEnable
unchanged.
1
Writing a 1 clears the corresponding bit in the Interrupt Enable
register, thus disabling interrupts for this request.
30
29
-
-
R/W
R/W
Rev. 01 — 12 January 2006
Section 5.4.4 "Interrupt Enable register (VICIntEnable -
28
27
-
TIMER3
WO
WO
20
19
-
I2C1
WO
WO
12
11
PLL
SSP/SPI1
WO
WO
4
3
TIMER0
ARMCore1
WO
WO
28
27
-
TIMER3
R/W
R/W
UM10161
Chapter 5: VIC
Section 5.4.5
26
25
TIMER2
-
WO
WO
18
17
AD0
-
WO
WO
10
9
SPI0
I2C0
WO
WO
2
1
ARMCore0
-
WO
WO
26
25
TIMER2
-
R/W
R/W
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Reset
value
0
24
-
WO
16
EINT2
WO
8
-
WO
0
WDT
WO
Reset
value
0
24
-
R/W
49
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