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Philips Semiconductors
ARM-based Microcontroller
POWER CONTROL
The LPC2119/2129/2292/2294 supports two reduced power modes: Idle mode and Power Down mode. In Idle mode, execution
of instructions is suspended until either a Reset or interrupt occurs. Peripheral functions continue operation during Idle mode and
may generate interrupts to cause the processor to resume execution. Idle mode eliminates power used by the processor itself,
memory systems and related controllers, and internal buses.
In Power Down mode, the oscillator is shut down and the chip receives no internal clocks. The processor state and registers,
peripheral registers, and internal SRAM values are preserved throughout Power Down mode and the logic levels of chip pins
remain static. The Power Down mode can be terminated and normal operation resumed by either a Reset or certain specific
interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Power Down mode
reduces chip power consumption to nearly zero.
Entry to Power Down and Idle modes must be coordinated with program execution. Wakeup from Power Down or Idle modes via
an interrupt resumes program execution in such a way that no instructions are lost, incomplete, or repeated. Wake up from Power
Down mode is discussed further in the description of the Wakeup Timer later in this chapter.
A Power Control for Peripherals feature allows individual peripherals to be turned off if they are not needed in the application,
resulting in additional power savings.
Register Description
The Power Control function contains two registers, as shown in Table 29. More detailed descriptions follow.
Table 29: Power Control Registers
Address
Name
0xE01FC0C0
PCON
0xE01FC0C4
PCONP
Power Control Register (PCON - 0xE01FC0C0)
The PCON register contains two bits. Writing a one to the corresponding bit causes entry to either the Power Down or Idle mode.
If both bits are set, Power Down mode is entered.
Table 30: Power Control Register (PCON - 0xE01FC0C0)
PCON
Function
0
IDL
1
PD
7:2
Reserved
System Control Block
Power Control Register. This register contains control bits that enable the two
reduced power operating modes of the LPC2119/2129/2292/2294. See Table 30.
Power Control for Peripherals Register. This register contains control bits that
enable and disable individual peripheral functions, Allowing elimination of power
consumption by peripherals that are not needed.
Idle mode - when 1, this bit causes the processor clock to be stopped, while on-chip
peripherals remain active. Any enabled interrupt from a peripheral or an external interrupt
source will cause the processor to resume execution.
Power Down mode - when 1, this bit causes the oscillator and all on-chip clocks to be
stopped. A wakeup condition from an external interrupt can cause the oscillator to re-
start, the PD bit to be cleared, and the processor to resume execution.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
LPC2119/2129/2292/2294
Description
Description
63
Preliminary User Manual
Access
R/W
R/W
Reset
Value
0
0
NA
January 08, 2004
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