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Philips Semiconductors
ARM-based Microcontroller
PIN DESCRIPTION
Pin Name
Type
Input/
D[31:0]
Output
A[23:0]
Output
OE
Output
BLS[3:0]
Output
WE
Output
CS[3:0]
Output
Table 6: External Memory Controller Pin Description
REGISTER DESCRIPTION
The external memory controller contains 4 registers as shown in Table 7.
Address
Name
0xFFE00000
BCFG0
0xFFE00004
BCFG1
0xFFE00008
BCFG2
0xFFE0000C
BCFG3
Table 7: External Memory Controller Register Map
Each register selects the following options for its memory bank:
• The number of idle clock cycles inserted between between read and write accesses in this bank, and between an access in
another bank and an access in this bank, to avoid bus contention between devices (1 to 17 clocks)
• the length of read accesses, except for subsequent reads from a burst ROM (3 to 35 clocks)
• the length of write accesses (3 to 19 clocks)
• whether the bank is write-protected
• whether the bank is 8, 16, or 32 bits wide
External Memory Controller (EMC)
External memory data lines.
External memory address lines.
Low-active Output Enable signal.
Low-active Byte Lane Select signals.
Low-active Write Enable signal.
Low-active Chip Select signals.
Configuration register for memory bank 0
Configuration register for memory bank 1
Configuration register for memory bank 2
Configuration register for memory bank 3
LPC2119/2129/2292/2294
Pin Description
Description
41
Preliminary User Manual
Access
Read/Write
Read/Write
Read/Write
Read/Write
January 08, 2004
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