Table 13.18 Relationship between Address and CE when Using PCMCIA Interface (cont)
Bus
Access
Width
Read/
Size
(Bits) *
(Bits)
Write
Dynamic
Read
8
bus
sizing *
2
16
Write
8
16
Read
8
16
Write
8
16
Notes: *1 In 32-bit/64-bit/32-byte transfer, the above accesses are repeated, with address
incrementing performed automatically according to the bus width, until the transfer data
size is reached.
*2 PCMCIA I/O card interface only
Odd/
1
Even
IOIS16 Access CE2 CE1 A0
Even
0
—
Odd
0
—
Even
0
—
Odd
0
—
Even
0
—
Odd
0
—
Even
0
—
Odd
0
—
Even
1
—
Odd
1
First
Odd
1
Second 1
Even
1
First
Even
1
Second 1
Odd
1
—
Even
1
—
Odd
1
First
Odd
1
Second 1
Even
1
First
Even
1
Second 1
Odd
1
—
D15–D8
1
0
0
Invalid
0
1
1
Read data
0
0
0
Upper read data Lower read data
—
—
—
—
1
0
0
Invalid
0
1
1
Write data
0
0
0
Upper write data Lower write data
—
—
—
—
1
0
0
Invalid
0
1
1
Ignored
0
1
Invalid
0
0
0
Invalid
0
1
Invalid
—
—
—
—
1
0
0
Invalid
0
1
1
Invalid
0
1
Invalid
0
0
0
Upper write data Lower write data
0
1
Invalid
—
—
—
—
Rev. 6.0, 07/02, page 447 of 986
D7–D0
Read data
Invalid
—
Write data
Invalid
—
Read data
Invalid
Read data
Lower read data
Upper read data
—
Write data
Write data
Write data
Upper write data
—