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12.1.4
Register Configuration
Table 12.2 summarizes the TMU registers.
Table 12.2 TMU Registers
Chan-
Abbre-
nel
Name
viation R/W
Com-
Timer
TOCR
mon
output
control
register
Timer
TSTR
start
register
TSTR2 *
Timer
start
register 2
0
Timer
TCOR0 R/W Ini-
constant
register 0
Timer
TCNT0 R/W Ini-
counter 0
Timer
TCR0
control
register 0
1
Timer
TCOR1 R/W Ini-
constant
register 1
Timer
TCNT1 R/W Ini-
counter 1
Timer
TCR1
control
register 1
2
Timer
TCOR2 R/W Ini-
constant
register 2
Timer
TCNT2 R/W Ini-
counter 2
Timer
TCR2
control
register 2
Input
TCPR2 R
capture
register
Initialization
Power-
On
Manual
Reset
Reset
R/W Ini-
Ini-
tialized
tialized
R/W Ini-
Ini-
tialized
tialized
3
R/W Ini-
Held
tialized
Ini-
tialized
tialized
Ini-
tialized
tialized
R/W Ini-
Ini-
tialized
tialized
Ini-
tialized
tialized
Ini-
tialized
tialized
R/W Ini-
Ini-
tialized
tialized
Ini-
tialized
tialized
Ini-
tialized
tialized
R/W Ini-
Ini-
tialized
tialized
Held
Held
Stand-
by
Mode
Initial Value P4 Address
Held
H'00
H'FFD80000 H'1FD80000 8
Ini-
H'00
H'FFD80004 H'1FD80004 8
1
tialized *
Held
H'00
H'FE100004 H'1E100004 8
Held
H'FFFFFFFF H'FFD80008 H'1FD80008 32
Held *
2
H'FFFFFFFF H'FFD8000C H'1FD8000C 32
Held
H'0000
H'FFD80010 H'1FD80010 16
Held
H'FFFFFFFF H'FFD80014 H'1FD80014 32
2
Held *
H'FFFFFFFF H'FFD80018 H'1FD80018 32
Held
H'0000
H'FFD8001C H'1FD8001C 16
Held
H'FFFFFFFF H'FFD80020 H'1FD80020 32
2
Held *
H'FFFFFFFF H'FFD80024 H'1FD80024 32
Held
H'0000
H'FFD80028 H'1FD80028 16
Held
Undefined
H'FFD8002C H'1FD8002C 32
Rev. 6.0, 07/02, page 293 of 986
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