10.2
Overview of CPG
10.2.1
Block Diagram of CPG
Figure 10.1 (1) shows a block diagram of the CPG in the SH7750 and SH7750S, and figure 10.1
(2) a block diagram of the CPG in the SH7750R.
Oscillator circuit
Crystal
XTAL
oscillator
EXTAL
MD8
CKIO
CPG control unit
MD2
MD1
MD0
FRQCR: Frequency control register
STBCR:
Standby control register
STBCR2: Standby control register 2
Figure 10.1 (1) Block Diagram of CPG (SH7750, SH7750S)
PLL circuit 1
× 6
Frequency
divider 1
× 1/2
PLL circuit 2
× 1
Clock frequency
control circuit
FRQCR
Bus interface
Internal bus
Frequency
divider 2
× 1
× 1/2
× 1/3
× 1/4
× 1/6
× 1/8
Standby control
circuit
STBCR
STBCR2
Rev. 6.0, 07/02, page 249 of 986
CPU clock (Iø)
cycle Icyc
Peripheral module
clock (Pø) cycle
Pcyc
Bus clock (Bø)
cycle Bcyc