Hitachi SH7750 Hardware Manual page 552

Sh7750 series superh risc engine

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DREQ Select (DS): Specifies either low level detection or falling edge detection as the

sampling method for the DREQ pin used in external request mode.

In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, it is valid in

CHCR0–CHCR3.

Note: Level detection burst mode when TM = 1 and DS = 0

Edge detection burst mode when TM = 1 and DS = 1

Bit 18—Request Check Level (RL): Selects whether the DRAK signal (that notifies an external

device of the acceptance of DREQ) is an active-high or active-low output.

In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, this bit is

Bit 17—Acknowledge Mode (AM): In dual address mode, selects whether DACK is output in the

data read cycle or write cycle. In single address mode, DACK is always output regardless of the

setting of this bit.

In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, this bit is

valid for CHCR1 to CHCR3 in the SH7750. In the SH7750S, this bit is valid for CHCR0 to

CHCR3. (DDT mode: TDACK)

Rev. 6.0, 07/02, page 502 of 986

Low level detection

Falling edge detection

DRAK is an active-high output

DRAK is an active-low output

DACK is output in read cycle

DACK is output in write cycle

(Initial value)

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