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Tc1
Tc2
Tc1
Tc2
Tc1
Tc2
Tc1
Tc2
Tce
CKIO
c1
c2
c3
c4
A25–A0
RD/
End of RAS down mode
D63–D0
d1
d2
d3
d4
(read)
DACKn
(SA: IO ← memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.22 (4) DRAM Burst Bus Cycle, RAS Down Mode Continuation
(EDO Mode, RCD = 0, AnW = 0)
Rev. 6.0, 07/02, page 408 of 986
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