Hitachi SH7750 Hardware Manual page 936

Sh7750 series superh risc engine
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Figure 22.24 Synchronous DRAM Auto-Precharge Read Bus Cycle: Burst
(RCD[1:0] = 01, CAS Latency = 3, TPC[2:0] = 011)
Rev. 6.0, 07/02, page 886 of 986

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