Interrupt-Request Codes; Table 14.17 Dtr Format For Clearing Request Queues - Hitachi SH7750 Hardware Manual

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DMAOR.DBL DTR.ID

Note: (SH7750R) DTR.SZ = DTR[63:61], DTR.ID = DTR[59:58], DTR.MD = DTR[57:56],

DTR.COUNT[7:4] = DTR[55:52]

Interrupt-Request Codes

When the number of transfers specified in DMATCR has been finished and the interrupt request is

enabled (CHCR.IE = 1), a transfer-end interrupt request can be sent to the CPU from each

channel. Table 14.18 lists the interrupt-request codes that are associated with these transfer-end

Rev. 6.0, 07/02, page 588 of 986

DTR.COUNT[7:4]

Clear the request queues of all channels

Clear the CH0 request-accepted flag

Setting prohibited

Clear the request queues of all channels

Clear the CH0 request-accepted flag.

Clear the CH0 request-accepted flag

Clear the CH1 request queues.

Clear the CH2 request queues.

Clear the CH3 request queues.

Clear the CH4 request queues.

Clear the CH5 request queues.

Clear the CH6 request queues.

Clear the CH7 request queues.

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