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Program
execution state
Interrupt
generated?
Yes
(BL bit
in SR = 0) or
(sleep or standby
mode)?
Yes
NMI?
Yes
Set interrupt source
in INTEVT
Save SR to SSR;
save PC to SPC
Set BL, MD, RB bits
in SR to 1
Branch to exception
handler
Note: * I3–I0: Interrupt mask bits in status register (SR)
No
No
No
Level 15
interrupt?
Yes
I3–I0 * =
Yes
level 14 or
lower?
No
Yes
Figure 19.3 Interrupt Operation Flowchart
No
NMIB in
ICR = 1 and
NMI?
Yes
No
No
Level 14
interrupt?
Yes
I3–I0 =
level 13 or
lower?
No
Yes
Rev. 6.0, 07/02, page 769 of 986
No
Level 1
interrupt?
Yes
I3–I0 =
level 0?
No
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